Method of making semiconductor memory device

ABSTRACT

A semiconductor memory device has plural first transistors constituting an information memory circuit and plural second transistors constituting gate units for controlling information input and output. The plural first transistors and the plural second transistors are formed in mutually overlaying structure across an insulating layer. A heterogeneous material of a nucleation density sufficiently higher than that of the insulating layer and of a size small enough to grow a single nucleus of a semiconductor material is formed on the insulating layer. The transistors positioned on the insulating layer are formed in a monocrystalline or substantially monocrystalline semiconductor layer grown around the single nucleus formed on the different material.

This application is a continuation of application Ser. No. 07/704,736filed May 20, 1991, now abandoned, which is a continuation ofapplication Ser. No. 07/426,529 filed Oct. 24, 1989, now abandoned,which is a continuation of application Ser. No. 07/115,977 filed Nov. 2,1987, now abandoned.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and moreparticularly to a semiconductor memory device having plural firsttransistors constituting an information memory circuit, and pluralsecond transistors constituting a gate circuit for controllinginformation input and output.

2. Related Background Art

Recent development of so-called information society has stimulated thedemand for memory devices, among which semiconductor memory devicesoccupy an important position due to their advantages performance andcost.

Among such semiconductor memory devices, there is already known a typehaving an information memory circuit for information storage and gateunits for controlling the writing and reading of said information.

FIG. 1 is a circuit diagram showing an example of a static RAM of saidtype.

As shown in FIG. 1, the static RAM cell is composed of an informationmemory circuit 20 and gate units 21a, 21b.

The information memory circuit 20 consists of MOS transistors T1, T3 andMOS transistors T2, T4 constituting CMOS inverters.

The gate units 21a, 21b are composed of MOS transistors T5, T6 forconnecting said information memory circuit 20 with read-out lines D, D,and the MOS transistors T5, T6 function as gate elements through gatesthereof connected to address lines AL.

In the manufacture of a semiconductor memory having an informationmemory circuit and gate units such as the static RAM mentioned above, ithas not been possible to overlay the information memory circuit and thegate units consisting of MOS transistors, since it is generallydifficult to form a monocrystalline semiconductor layer on an insulatinglayer. For this reason the information memory circuit and the gate unitsare placed side by side on a same conductive substrate, and the readingline and the address line are placed on an insulating layer.Consequently the density of integration can only be improved byoverlaying the reading line and the address line in the wiring area, anda sufficient degree of integration has therefore been difficult toachieve.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a semiconductor memorydevice with an improved density of integration achieved by overlayingthe transistors of the information memory circuit and/or the gate unitsacross an insulating layer. According to the present invention, theabove-mentioned object can be achieved by providing, on an insulatinglayer, a heterogeneous material of a nucleation density sufficientlyhigher than that of said insulating layer and of a size sufficientlysmall to allow the growth of a single nucleus of a semiconductormaterial, and forming, on a monocrystalline or substantiallymonocrystalline semiconductor layer grown around said single nucleus ofsaid different material, a transistor or transistors of the informationmemory circuit and the gate units, to be placed on said insulatinglayer. Consequently there is obtained a semiconductor memory device of ahigh degree of integration and of performance comparable to the casewhere the transistors are formed side by side on a same surface of asemiconductor substrate.

The steps for forming said monocrystalline or substantiallymonocrystalline semiconductor layer on said insulating layer are thesame as those already known in the conventional semiconductor processesas will be explained later. These processes do not contain specialsteps.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of an example of a static RAM;

FIG. 2 is a schematic partial cross-sectional view of an embodiment ofthe semiconductor memory device of the present invention;

FIG. 3 is a circuit diagram of a memory cell of said semiconductormemory device;

FIGS. 4A and 4B are schematic views showing the principle of selectivedeposition process;

FIG. 5 is a chart showing time-dependent change of nucleus formationdensity on a deposited surface of SiO₂ and on a deposited surface ofsilicon nitride;

FIGS. 6A to 6D are views showing steps for forming a monocrystalline orsubstantially monocrystalline layer;

FIGS. 7A and 7B are perspective views of the substrate respectively atthe steps shown in FIGS. 6A and 6D;

FIG. 8 is a chart showing the relationship between the flow rate ratioof SiH₄ and NH₃, and the ratio of Si and N in the resulting siliconnitride film;

FIG. 9 is a chart showing the relationship between the ratio of Si/N andthe nucleation density; and

FIG. 10 is a chart showing the relationship between the amount of Si ionimplantation and the nucleation density.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

An embodiment of the present invention is described in detail, withreference to the attached drawings, as follows.

FIG. 2 is a schematic partial cross-sectional view of the embodiment ofthe semiconductor memory device of the present invention, and FIG. 3 isa circuit diagram of a memory cell of said device.

As shown in FIG. 3, the information memory circuit 20 of the presentembodiment is composed of two CMOS inverters 12, 13 constituting astatic RAM equivalent to that shown in FIG. 1. The input of the CMOSinverter 12 is connected to the output of the CMOS inverter 13, and tothe sources of MOS transistors 181, 182, 183 of a gate unit 21b.Similarly the input of the CMOS inverter 13 is connected to the outputof the CMOS inverter 12, and to the sources of MOS transistors 171, 172,173 of a gate unit 21a. The gates of the MOS transistors 181, 182, 183of the gate unit 21b are connected to address lines AL1, AL2, AL3, andthe drains are connected to reading lines D1, D2, D3. Similarly thegates of the MOS transistors 171, 172, 173 of the gate unit 21a areconnected to address lines AL1, AL2, AL3, and the drains are connectedto reading lines D1, D2, D3.

The address lines AL1, AL2, AL3 control the MOS transistors 171, 172,173 of the gate unit 21a and the MOS transistors 181, 182, 183 of thegate unit 21b, thereby controlling the information writing and readingof the information memory circuit 20.

In the present embodiment plural MOS transistors 171-173, 181-183 areconnected to the information memory circuit 20. By increasing the numberof MOS transistors in the gate units 21a, 21b, the semiconductor memorydevice can be used in more different applications.

In the following there will be given the process of producing thesemiconductor memory device explained above.

At first, as shown in FIG. 2, a p-channel MOS transistor 2 and ann-channel MOS transistor 3 are formed by a known semiconductor processon an n-silicon substrate, thus constituting CMOS transistors. Theelements are mutually separated by a field insulating layer 4. An SiO₂layer 5 constituting an insulating layer is formed on said CMOStransistors, on which Si₃ N₄ films 6, 7, constituting a differentmaterial, are formed. Subsequently a monocrystalline or substantiallymonocrystalline silicon layer are grown around said Si₃ N₄ layers 6, 7by a process to be explained later. Said layer growth is conducted at atemperature of 700° to 1000° C. with a gas such as SiH₄, SiCl₄ orSiHCl₃, utilizing hydrogen as carrier gas. The ratio N of the siliconnucleation density B on the Si₃ N₄ films 6, 7 to the nucleation densityA on the SiO₂ layer 5 can be made equal to B/A=10⁴ or even larger underthe above-mentioned conditions.

As the monocrystalline or substantially monocrystalline silicon layerhas a polygonal shape after formation thereof, it is made flat by anintegrated circuit technology such as an etch-back process. After saidflattening, a conventional process for producing semiconductor devicesis utilized to form a source area 8, a drain area 9 and a gate electrode11 on a gate insulating layer 10, thereby forming MOS transistors 15, 16constituting gate units. The connections with the underlying CMOStransistors are made by a wiring 19 through a contact hole 12. Ifadditional MOS transistors are required for the gate units, aninsulating layer 13 is formed on the MOS transistors 15, 16, and MOStransistors are formed thereon in similar manner and connected with theCMOS transistors positioned thereunder by a through hole 14 in theinsulating layer 13.

In the above-explained embodiment, the MOS transistors constituting thegate units 21a, 21b are formed, across the insulating layer, on the CMOStransistors constituting the information memory circuit, but it is alsopossible to form the CMOS transistors constituting said memory circuit20 on the MOS transistors constituting the gate units.

In the following there will be given a detailed explanation on theprocess for forming the monocrystalline or substantially monocrystallinesemiconductor layer.

At first there will be given a selective deposition method, whichselectively forms a thin film on a substrate, utilizing the difference,among various materials, of the factors influencing the nucleation inthe film forming process, such as the surface energy, adhesioncoefficient, elimination coefficient, surface diffusion speed etc.

FIGS. 4A and 4B schematically illustrate the selective depositionmethod. At first, as shown in FIG. 4A, there is formed, on a substrate101, a thin film 102 of a material different in said factors from thesubstrate 101 in a desired area. Then a thin film of a suitable materialis deposited, and under suitable conditions it is possible to grow thethin film 103 only on the thin film 102 but not on the substrate 101.Such phenomenon enables the growth of a self-aligned thin film 103, thusdispensing with a conventional photolithographic process utilizingphotoresist.

Examples of the materials employable in such selective deposition methodare SiO₂ for the substrate 101, Si, GaAs or silicon nitride for the thinfilm 102, and Si, W, GaAs or InP for the thin film 103 to be deposited.

FIG. 5 is a chart showing the time-dependent change of the nucleationdensity on the deposited SiO₂ surface and on the deposited siliconnitride surface.

As shown in said chart, the nucleation density on SiO₂ becomes saturatedat a level under 10³ cm⁻² soon after the start of deposition, and thedensity scarcely changes even after 20 minutes from the start.

On the other hand, on silicon nitride (Si₃ N₄), the nucleation densityis once saturated at a level about 4×10⁵ cm⁻² and retains said level forabout 10 minutes, but rapidly increases thereafter. In this example thedeposition was conducted by CVD method at a pressure of 175 Torr and atemperature of 1000° C., utilizing SiCl₄ gas diluted with H₂ gas. Alsosimilar results can be achieved with another reaction gas such as SiH₄,SiH₂ Cl₂, SiHCl₃ or SiF₄ under suitably regulated pressure andtemperature. Also vacuum evaporation can be used for this purpose.

In this case the nucleation on SiO₂ is negligibly small, but theaddition of HCl gas to the reaction gas further suppresses thenucleation on SiO₂, and completely eliminates the Si deposition on SiO₂Such phenomenon is principally ascribable to the difference, betweenSiO₂ and silicon nitride, in the absorption coefficinet, peelingcoefficient, surface diffusion speed etc. to silicon, but the selectivedeposition is also caused by a fact that silicon atoms react with SiO₂to generate silicon monoxide of a high vapor pressure, thereby etchingSiO₂ itself, whereas such etching phenomenon does not occur on siliconnitride (T. Yonehara, S. Yoshioka, S. Miyazawa, Journal of AppliedPhysics 53, 6839, 1982).

As shown in FIG. 5, a sufficiently large difference in nucleationdensity can be obtained by employing SiO₂ and silicon nitride for thesurface to be subjected to deposition, with silicon as the depositingmaterial. Though SiO₂ is preferred for the surface receiving thedeposition, a difference in the nucleation density can also be obtainedwith SiO_(x).

Naturally the present invention is not limited to these materials, but adifference in the nucleation density in excess of 10³ is enough as shownin FIG. 5 and allows sufficient selective deposition even with thematerials to be explained later.

Said difference in the nucleation density may also be obtained by localion implantation of Si or N on SiO₂ for forming areas having an excessin Si or N.

Such selective deposition method can be utilized for forming a differentmaterial of a nucleation density sufficiently larger than that of thematerial of the depositing surface, in such a small size as to allowgrowth of a single nucleus, and selectively growing thereon a singlecrystal or a substantially single crystal only in the position of saidsmall different material.

Since the selective growth of said single crystal or substantiallysingle crystal is determined by the state of electrons on the depositingsurface, particularly the state of dangling bonds, the material of lowernucleation density, for example SiO₂, need not be a bulk material butcan be formed on an arbitrary material or substrate.

FIGS. 6A to 6D illustrate steps of an example of the method for formingsaid single crystal or substantially single crystal. FIGS. 7A and 7B areperspective views of a substrate respectively in the steps shown inFIGS. 6A and 6D.

At first, as shown in FIGS. 6A and 7A, a thin film 105 of a, lownucleation density enabling selective deposition is formed on asubstrate 104. Then a different material of a higher nucleation densityis thinly deposited on said thin film 105 and patterned for example by alithographic process in a sufficinetly small size, as indicated by 106.The substrate 104 can be of arbitrary size, crystal structure andcomposition, and may have functional device thereon. Also said differentmaterial 106 can be a modified area having an excess in Si or N, formedby ion implantation thereof into the thin film 105 as explained above.

Then, under suitable depositing conditions, a single nucleus of a thinfilm material is formed only on the different material 106. Stateddifferently, the different material 106 has to be formed so small as toallow growth of a single nucleus only. For this purpose, the size of thedifferent material 106 should be several microns or smaller, though itdepends on the material to be used. The nucleus grows, maintaining themonocrystalline or substantially monocrystalline structure, to form anisland-shaped monocrystalline particle 107 as shown in FIG. 6B, and, asalready explained before, complete absence of nucleation on the thinfilm 105 is indispensable for obtaining such particle 107.

The island-shaped monocrystalline particle 107 further grows,maintaining the monocrystalline or substantially monocrystallinestructure, to eventually cover the entire thin film 105 as shown in FIG.6C.

Subsequently the monocrystalline particle 107 is flattened by etching orlapping to obtain, as shown in FIGS. 6D and 7B, a monocrystalline layer108 enabling formation of desired devices, on the thin film 105.

Due to the presence of the thin film 105 constituting the depositingsurface, the underlying substrate 104 can be composed of an arbitrarymaterial. Thus a monocrystalline or substantially monocrystalline layercan be easily formed even if the substrate has functional devicesthereon.

In the foregoing embodiment the depositing surface is composed of a thinfilm 105, but it is also possible to employ a substrate composed of amaterial of a low nucleation density enabling selective deposition andto form a monocrystalline or substantially monocrystalline layerthereon.

EXAMPLE

In the following there will be given more detailed examples of themethod of forming the monocrystalline layer in the foregoing embodiment.

SiO₂ is employed as the thin film 105 constituting the depositingsurface. Naturally there may be employed a quartz substrate, or a SiO₂layer may be formed by sputtering, CVD or vacuum evaporation on anarbitrary substrate composed for example of metal, semiconductor,magnetic material, piezoelectric material or insulating material. Thoughthe depositing surface is preferably composed of SiO₂, it may also becomposed of SiO_(x) with a different value of x.

On the SiO₂ layer 105 thus formed, a silicon nitride (Si₃ N₄) layer or apolycrystalline silicon layer is deposited by gaseous growth as thedifferent material, and is patterned with an ordinary lithographicprocess or a lithographic process utilizing X-ray, an electron beam oran ion beam to form the small different material 106 not exceedingseveral microns, preferably about 1 micron, in size.

Then Si is selectively grown on the substrate with a gaseous mixture ofHCl, H₂ and SiH₂ Cl₂, SiCl₄, SiHCl₃, SiF₄ or SiH₄, with a substratetemperature of 700°-1000° C. and a pressure of ca. 100 Torr.

Within a period of several tens of minutes, a monocrystalline siliconparticle 107 grows around the small different material 106 composed ofsilicon nitride or polycrystalline silicon on SiO₂, even to a size ofseveral tens of microns under optimum conditions.

Subsequently reactive ion etching (RIE) having an etch rate differencebetween Si and SiO₂ is conducted to flatten silicon, thereby obtaining apolycrystalline silicon layer of controlled particle size. Then theparticle boundary portions are removed to obtain an island-shapedmonocrystalline silicon layer 108. If the monocrystalline particle 107has an irregular surface, the etching is conducted after mechanicallapping.

Thus formed monocrystalline silicon layer 108, of several tens ofmicrons in size and free from particle boundaries, enables formation offield effect transistors comparable in performance to those formed on amonocrystalline silicon wafer.

Also it is electrically separated by SiO₂ from the neighboringmonocrystalline silicon layer 108, so that CMOS transistors formedtherein are free from mutual interference. Besides, as the active layerof the device is thinner than that formed in a silicon wafer, it ispossible to prevent erroneous operation caused by a charge induced by anirradiation. Furthermore a lower parasite capacitance results in ahigher operating speed of the device. Also the possibility of using anarbitrary substrate allows the monocrystalline layer to form on a largersubstrate with a lower cost than in case of silicon wafer. Furthermoreit is rendered possible to obtain a multifunctional three-dimensionalintegrated circuit as the monocrystalline layer can be formed on asubstrate composed of a semiconductive material, a piezoelectricmaterial or a dielectric material.

Composition of Silicon Nitride

A sufficiently large difference in the nucleation density between thematerial constituting the depositing surface and the different material,as explained before, can be obtained not only with Si₃ N₄ but also withsilicon nitride of different composition.

In the formation of the silicon nitride film with plasma CVD bydecomposing SiH₄ gas and NH₃ gas in RF plasma at a low temperature, theratio of Si to N in the deposited silicon nitride film can besignificantly varied by a change in the flow rate ratio of SiH₄ gas andNH₃ gas.

FIG. 8 shows Si/N composition ratio in the deposited silicon nitridefilm as a function of the flow rate ratio of SiH₄ and NH₃.

In this example the deposition was conducted with an RF output of 175 Wand a substrate temperature of 380° C., and with a fixed flow rate ofSiH₄ gas at 300 cc/min and a varying flow rate of NH₃ gas. In responseto a change in the NH₃ /SiH₄ flow rate ratio from 4 to 10, the Si/Nratio in the silicon nitride film, determined by electron spectroscopyshows a change from 1.1 to 0.58.

On the other hand, a silicon nitride film formed with a reduced pressureCVD method by introducing SiH₂ Cl₂ gas and NH₃ gas at a pressure of 0.3Torr and a temperature of ca. 800° C. showed a composition close to thestoichiometric ratio of Si₃ N₄ (Si/N=0.75).

Also a silicon nitride film formed by thermal treatment of Si withammonia or N₂ at ca. 1200° C. (thermal nitrization) showed a compositioneven closer to the stoichiometric ratio, as the film formation wasachieved under thermal equilibrium.

Such silicon nitrides obtained in various methods, when used in siliconnuclei growth as the material having a higher nucleation density,provide a nucleation density variable according to the compositionratio.

FIG. 9 shows the nucleation density as a function of the Si/Ncomposition ratio. As shown in FIG. 9, a change in the composition ofsilicon nitride film significantly varies the density of silicon nucleideveloped thereon. The Si nucleation was conducted by reacting SiCl₄ of175 Torr with H₂ at 1000° C.

This phenomenon of the change in the nucleation density as a function ofthe composition of silicon nitride influences the size of siliconnitride formed sufficiently small for growing a single nucleus. Stateddifferently, silicon nitride of a composition of a large nucleationdensity cannot grow a single nucleus unless the particle is formed verysmall.

It is therefore necessary to select the nucleation density and theoptimum size of silicon nitride allowing single nucleus formation. Forexample, under depositing conditions providing a nucleation density ofca. 10⁵ cm⁻², single nucleus formation can be achieved if the size ofsilicon nitride is ca. 4 μm or smaller.

Formation of Heterogeneous Material by Ion Implantation

A difference in nucleation density from Si can also be realized by localion implantation of Si, N, P, B, F, Ar, He, C, As, Ga, Ge etc. on thesurface of SiO₂ constituting a depositing surface of low nucleationdensity to form modified areas thereon, and utilizing said modifiedareas as the depositing surface of high nucleation density.

As an example, the surface of SiO₂ is covered with photoresist, and ispartially exposed to the outside in desired areas by exposing anddeveloping the photoresist in said areas.

Then Si ions are implanted, from SiF₄ source gas, into the SiO₂ surfacewith a voltage of 10 keV and with a density of 1×10¹⁶ to 1×10¹⁸ cm⁻².The projection stroke is 114 Å, and the Si concentration at the SiO₂surface reaches as high as ca. 10²³ cm⁻². The ion implanted area isamorphous as SiO₂ is originally amorphous.

The modified area can be obtained by ion implantation utilizingphotoresist as explained above, or by ion implantation of Si ions intothe SiO₂ surface with a concentrated ion beam and without photoresist.

After such ion implantation, the photoresist is removed to obtain amodified area with an excess in Si, on the SiO₂ surface. Then silicon isgrown in gaseous phase on the SiO₂ depositing surface, having suchmodified areas.

FIG. 10 shows the nucleation density as a function of the amount ofimplanted Si ions. As shown in FIG. 10, the nucleation density increaseswith the increase in the amount of implanted Si ions.

It is therefore possible to grow a single silicon nucleus on saidmodified area, functioning as the different material, by forming saidmodified area sufficiently small, and therefore to grow a single crystalas explained above.

A sufficiently small modified area allowing a single nucleus growth canbe easily obtained by a patterning with photoresist or by concentratingthe ion beam.

Silicon Deposition Other Than CVD

Monocrystalline growth by selective silicon nucleus formation can beachieved not only by CVD but also by evaporating silicon with anelectron gun in vacuum (<10⁻⁶ Torr) and depositing on a heatedsubstrate. Particularly in molecular beam epitaxy (MBE) utilizingevaporating in ultra high vacuum (<10⁻⁹ Torr) it is known that the Sibeam and SiO₂ start to react at a substrate temperature of 900° C. orhigher to completely eliminate Si nucleation on SiO₂ (T. Yonehara, S.Yoshioka and S. Miyazawa, Journal of Applied Physics 53, 10, p. 6839,1982).

This phenomenon could be utilized in forming a single silicon nucleuswith complete selectivity in each of scattered small silicon nitrideareas on SiO₂ and growing monocrystalline silicon thereon. Thedeposition was conducted under vacuum of 10⁻⁸ Torr or lower, a Si beamintensity of 9.7×10¹⁴ atoms/cm². sec and a substrate temperature of 900°to 1000° C.

In this case a reaction SiO₂ +Si→2SiO↑ generates a reaction product SiOwith a very high vapor pressure, with the resulting etching of SiO₂itself by Si.

On the other hand silicon nitride does not cause such etching butnucleation and deposition thereon.

Consequently similar results can be obtained tantalum oxide (Ta₂ O₅) orsilicon oxynitride (SiON) instead of silicon nitride, as the materialwith high nucleation density. More specifically, similar monocrystallinegrowth can be achieved by forming these materials in a small form as thedifferent material explained above.

The above-explained single crystal growing method enables formation of asemiconductor crystal layer on an insulating layer.

The above-explained single crystal growing of transistors constitutingan information memory circuit with those constituting gate units,thereby enabling a higher degree of integration and providing asemiconductor memory device of a high capacity.

Also in the present embodiment, a laminate structure of the transistorsconstituting gate units allows formation of a larger number ofinput-output control transistors within a same area, thereby providing asemiconductor memory device usable for multiple purposes.

What is claimed is:
 1. A method for producing a semiconductor memorydevice comprising a first plurality of transistors constituting aninformation memory circuit and a second plurality of transistorsconstituting gate units for controlling information input to and outputfrom the information memory circuit, the first plurality of transistorsand the second plurality of transistors being formed in mutuallyoverlying structure across an insulating layer, the method comprisingforming either the first plurality of transistors or the secondplurality of transistors by a process comprising the steps of:forming afirst material, having a nucleation density sufficiently higher thanthat of the insulating layer, on the insulating layer in a sufficientlysmall area so as to form only a single nucleus from which a singlecrystal of a semiconductor material is grown; and growing a layer ofmonocrystalline semiconductor material, different from the firstmaterial, by a vapor phase process around a single nucleus grown fromthe first material.
 2. A method for producing a semiconductor memorydevice according to claim 1, wherein only the second plurality oftransistors are formed by said process.
 3. A method for forming asemiconductor memory device comprising a first plurality of transistorsconstituting an information memory circuit and a second plurality oftransistors constituting gate units for controlling information input toand output from said information memory circuit, said method comprisingthe steps of:forming an insulating layer on a substrate having saidfirst plurality of transistors; forming a first material having anucleation density sufficiently higher than that of said insulatinglayer in a small enough area so as to form only a single nucleus fromwhich a single crystal of a semiconductor material is grown; and growinga layer of monocrystalline semiconductor material, different from saidfirst material, by applying vapor deposition around a single nucleusgrown from said first material.